Title: Models and Verified System Design
Michael Butler

Abstract

Verified system design is concerned not just with software correctness, but the 
correct design of a system as a whole, including its software parts. Verified 
system design is feasible using a formal language that supports modelling at 
many levels of abstraction and provides effective refinement verification 
between these levels. Powerful tools are required to support the construction 
and evolution of chains of models linked by refinement.